1. Field of Invention
The present invention relates to a method for manufacturing integrated circuits. More particularly, the present invention relates to a method for manufacturing a dynamic random access memory (DRAM) capacitor.
2. Description of Related Art
As the microprocessor of a computer becomes more powerful, the amount of software programs that can be simultaneously run inside a computer increases exponentially. Consequently, the amount of memory space necessary for storing data must be increased, and so highly efficient memory capacitors are in great demand. As the level of integration of DRAM increases, DRAM cells are now constructed from just one transfer field effect transistor and a storage capacitor. FIG. 1 is an equivalent circuit diagram of a DRAM cell. A DRAM is normally constructed from an array of these cells. A binary bit is stored in the capacitor C of each cell. In general, when the capacitor C is uncharged, a logic state of "0" is defined. On the other hand, when the capacitor C is fully charged, a logic state of "1" is defined. A capacitor C has an upper electrode (cell electrode) 100 and a lower electrode (storage electrode) 102 with a layer of dielectric 101 sandwiched between the two to provide the necessary dielectric constant. In addition, the capacitor C is coupled to a bit line (BL), and reading and writing to and from the DRAM memory is achieved by charging or discharging the capacitor C. Charging and discharging of the capacitor C is carried out through the control of a transfer field effect transistor (TFET). The source terminal of the transfer transistor is connected to the bit line BL while the drain terminal of the transfer transistor is connected to the capacitor C. The transfer transistor T is switched on or off through a selection signal coming from a word line WL, which is connected to the gate terminal of the transfer transistor T. Hence, whether the capacitor C is connected to the bit line allowing for charging or discharging of the capacitor depends upon the selection signal passed to the gate terminal.
The capacitor can be regarded as the heart of a DRAM device. When the quantities of electric charges stored in a capacitor are increased, data amplified out from memory will be less affected by noise surrounding the communication system. In general, the charge storage capacity of a capacitor can be increased in several ways, including: 1) choosing a material having a high dielectric constant to form the dielectric film layer; 2) reducing the thickness of the dielectric film layer; and 3) increasing the surface area of a capacitor. Nowadays, many materials with high dielectric constant have been developed including tantalum pentoxide (Ta.sub.2 O.sub.5), Pb(Zr,Ti)O.sub.3 or PZT and (Ba,Sr)TiO.sub.3 or BST. To increase the surface area of a capacitor, three-dimensional capacitors such as the so-called stacked type and trench type are now commonly used. For a 64 Mbit DRAM, for example, one method of further increasing the surface area of a capacitor is to extend the electrode and dielectric film layer horizontally and then stack the layers up to form a fin-type stacked capacitor. An alternative method is to allow the electrode and the dielectric film layer to extend vertically up to form a cylindrical-type stacked capacitor. Description related to the formation of a fin-type capacitor can be found in an article by Ema et al. with the title "3-Dimensional Stacked Capacitor Cell for 16M and 64M DRAMs", published in International Electron Devices Meeting, pp 592-595, December 1988, or U.S. Pat. No. 5,071,783, U.S. Pat. No. 5,126,810 and U.S. Pat. No. 5,206,787. Description related to the formation of a cylindrical-type capacitor can be found in another article by Wakamiya et al. with the title "Novel Stacked Capacitor Cell for 64 Mb DRAM", published in Symposium on VLSI Technology Digest of Technical Papers, pp 69-70, 1989, or U.S. Pat. No. 5,077,688.
FIGS. 2A through 2E are cross-sectional views showing the progression of manufacturing steps in forming a conventional cylindrical type DRAM capacitor. First, as shown in FIG. 2A, a DRAM field effect transistor 201 is formed over a substrate 200, for example, a P-type silicon substrate. The field effect transistor 201 includes a gate structure 203 and source/drain regions 208 and 209, and are formed in the active device region of the substrate 200 insulated from other regions by a field oxide layer 202. Next, a first dielectric layer 210 and a second dielectric layer 212 are sequentially formed over the substrate 200. The first dielectric layer 210 can be a borophosphosilicate glass (BPSG) layer formed, for example, by an atmospheric pressure chemical vapor deposition (APCVD) method. The second dielectric layer 212 can be a tetra-ethyl-ortho-silicate glass (TEOS) silicon oxide layer formed, for example, by an atmospheric pressure chemical vapor deposition (APCVD) method using TEOS as gaseous reactant. Alternatively, the first dielectric layer 210 can be a TEOS silicon oxide layer and the second dielectric layer 212 can be a BPSG layer.
Next, as shown in FIG. 2B, conventional photolithographic and etching processes are used to pattern the first dielectric layer 210 and the second dielectric layer 212. Consequently, a contact window 214 and a wide opening 216 exposing source/drain region 208 are formed.
Next, as shown in FIG. 2C, a conductive material, for example, a doped polysilicon layer, is deposited over the substrate 200 and the wide opening 216 and into the contact window 214 forming a conductive layer 218. The conductive layer 218 is electrically coupled to the source/drain region 208 and serves as a storage electrode for the capacitor.
Thereafter, as shown in FIG. 2D, the conductive layer 218 is planarized, for example, by a chemical-mechanical polishing (CMP) operation. The conductive layer 218 is polished to expose the second dielectric layer 212. Then, the second dielectric layer 212 is removed to expose the outer portion of the conductive layer 218 using, for example, an isotropic etching process. Subsequently, a dielectric film layer 220, preferably having a thickness of about 10 .ANG. to 60 .ANG., is formed over the exposed conductive layer 218. The dielectric film layer 220 can be a silicon oxide layer, a silicon nitride/silicon oxide (NO) composite layer, a silicon oxide/silicon nitride/silicon oxide (ONO) composite layer, or composed from high dielectric constant materials such as tantalum pentoxide (Ta.sub.2 O.sub.5), Pb(Zr,Ti)O.sub.3 or PZT and (Ba,Sr)TiO.sub.3 or BST.
Finally, as shown in FIG. 2E, another conductive layer 222 is formed over the dielectric film layer 220. The conductive layer 222 functions as a cell electrode of the capacitor. In general, when the dielectric film layer 220 is made from high dielectric constant material such as tantalum pentoxide, the conductive layer 222 can be made from a highly conductive titanium nitride (TiN) material. The titanium nitride layer can be deposited over the dielectric film layer 220 using, for example, a physical vapor deposition method. After the formation of the conductive layer 222, the processing steps necessary for fabricating a conventional DRAM capacitor are complete.
In the above conventional method of fabrication, when the second dielectric layer 212 is removed by etching in order to expose the conductive layer 218, over-etching will often occur around area 230 as shown in FIG. 2D. To better describe the problems caused by over-etching a more detailed view of the area 230 is shown in FIG. 2F. FIG. 2F is a magnified view of the area enclosed inside the dashed rectangle of FIG. 2D. Since any residual second dielectric layer on the conductive layer 218 is undesirable and may lead to subsequent electrical problems, over-etching is often preferred. However, over-etching may result in damages to the first dielectric layer 210 as shown in the recess area 230 in FIG. 2F. Furthermore, the corner space 230a in the recess area 230 will make subsequent deposition of dielectric film layer 220 and conductive upper electrode layer 222 incomplete, thereby leading to current leakage.
In another aspect, the above method of fabrication uses a physical vapor deposition method to achieve the formation of a titanium nitride layer acting as a cell electrode. However, due to the increase in level of integration, using physical vapor deposition cannot provide the kind of step coverage necessary for a good deposition resulting in a configuration as shown in FIG. 2E. Hence, a method having a better step-coverage such as chemical vapor deposition (CVD) is employed to deposit the titanium nitride layer. For example, a metal-organic CVD (MOCVD) method can be used to deposit titanium nitride over a tantalum pentoxide dielectric film. Alternatively, a CVD method can be used to deposit titanium nitride over a tantalum pentoxide dielectric film by first reacting it with the reactive gas titanium tetrachloride (TiCl.sub.4) at a temperature of about 500.degree. C., and then followed by heating it to about 850.degree. C. in the presence of gaseous nitrogen to anneal the titanium nitride layer. However, in practice, the titanium nitride layer formed by the MOCVD method can easily be contaminated by carbon in the gaseous source, while the titanium nitride layer formed by the CVD technique of deposition is contaminated by the chlorine derived from the reactive gas (titanium tetrachloride).
FIGS. 3A and 3B show X-ray photoelectron spectroscopy (XPS) depth profiles before and after annealing a titanium nitride layer above the tantalum pentoxide dielectric film using a temperature of about 850.degree. C. in the presence of gaseous nitrogen, where the titanium nitride layer is first deposited over the tantalum pentoxide by a CVD method using titanium tetrachloride as the reactive gas at a temperature of about 500.degree. C. From the profile shown in FIGS. 3A and 3B, cross-diffusion between the titanium nitride layer and the tantalum pentoxide dielectric film is severe, thereby providing an additional source of current leakage from the device.
In light of the foregoing, there is a need provide an improved method of fabricating a DRAM capacitor.